Date of Award

Spring 5-2026

Document Type

Thesis

Department

Electrical Engineering and Computer Science

First Advisor

Dr. Tom Springer

Second Advisor

Dr. Peiyi Zhao

Third Advisor

Dr. Mark Harrison

Abstract

We present a full-system co-simulation platform for evaluating embedded machine learning (ML) inference using compute-in-memory (CIM). CIM architectures aim to reduce data movement overhead by performing matrix operations in memory, but end-to-end benefits depend on system-level integration costs that are difficult to assess with isolated hardware models alone. To address this gap, we develop an integrated RISC-V QEMU-SystemC co-simulation environment that allows standard embedded Linux to interact with a transaction-level CIM accelerator model via memory-mapped I/O, direct memory access (DMA), and interrupts. To evaluate performance, we benchmark an MNIST image inference workload and a synthetic fully connected neural network, comparing CPU-only execution with CIM-offloaded execution. For MNIST, CIM reduces CPU instruction count by 88.6% and estimated total system dynamic energy by 84.0%. Furthermore, stress-testing with the large synthetic topology demonstrates that these efficiency gains scale considerably as the CPU encounters the memory wall. Ultimately, the co-simulation framework provides a practical, full-stack approach for studying CIM integration trade-offs in embedded ML systems and for identifying when CIM-offload becomes beneficial under realistic constraints on software and device interactions.

DOI

10.36837/chapman.000735

Creative Commons License

Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial-Share Alike 4.0 License.

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