Document Type
Conference Proceeding
Publication Date
3-9-2023
Abstract
In the modern graphics processing unit (GPU)/artificial intelligence (AI) era, flip-flop (FF) has become one of the most power-hungry blocks in processors. To address this issue, a novel single-phase-clock dual-edge-triggering (DET) FF using a single-transistor-clocked (STC) buffer (STCB) is proposed. The STCB uses a single-clocked transistor in the data sampling path, which completely removes clock redundant transitions (RTs) and internal RTs that exist in other DET designs. Verified by post-layout simulations in 22 nm fully depleted silicon on insulator (FD-SOI) CMOS, when operating at 10% switching activity, the proposed STC-DET outperforms prior state-of-the-art low-power DET in power consumption by 14% and 9.5%, at 0.4 and 0.8 V, respectively. It also achieves the lowest power-delay-product (PDP) among the DETs.
Recommended Citation
Z. Wang et al., "Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, https://doi.org/10.1109/TVLSI.2023.3251286.
Copyright
© 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Comments
This is a pre-copy-editing, author-produced PDF of an article accepted for publication in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, volume 31, issue 5, in 2023. https://doi.org/10.1109/TVLSI.2023.3251286