Document Type
Article
Publication Date
5-8-2019
Abstract
Deep Learning (DL) offers the advantages of high accuracy performance at tasks such as image recognition, learning of complex intelligent behaviors, and large-scale information retrieval problems such as intelligent web search. To attain the benefits of DL, the high computational and energy-consumption demands imposed by the underlying processing, interconnect, and memory devices on which software-based DL executes can benefit substantially from innovative hardware implementations. Logic-in-Memory (LIM) architectures offer potential approaches to attaining such throughput goals within area and energy constraints starting with the lowest layers of the hardware stack. In this paper, we develop a Spintronic Logic-in-Memory (S-LIM) XNOR neural network (S-LIM XNN) which can perform binary convolution with reconfigurable in-memory logic without supplementing distinct logic circuits for computation within the memory module itself. Results indicate that the proposed S-LIM XNN designs achieve 1.2-fold energy reduction, 1.26-fold throughput increase, and 1.4-fold accuracy improvement compared to the state-of-the-art binarized convolutional neural network hardware. Design considerations, architectural approaches, and the impact of process variation on the proposed hybrid spin-CMOS design are identified and assessed, including comparisons and recommendations for future directions with respect to LIM approaches for neuromorphic computing.
Recommended Citation
A. Samiee, P. Borulkar, R. F. DeMara, P. Zhao and Y. Bai, "Low-Energy Acceleration of Binarized Convolutional Neural Networks Using a Spin Hall Effect Based Logic-in-Memory Architecture," in IEEE Transactions on Emerging Topics in Computing, vol. 9, no. 2, pp. 928-940, 1 April-June 2021, https://doi.org/10.1109/TETC.2019.2915589.
Copyright
© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Included in
Hardware Systems Commons, Other Computer Engineering Commons, Other Computer Sciences Commons
Comments
This is a pre-copy-editing, author-produced PDF of an article accepted for publication in IEEE Transactions on Emerging Topics in Computing, volume 9, issue 2, in 2021 following peer review. This article may not exactly replicate the final published version. The definitive publisher-authenticated version is available online at https://doi.org/10.1109/TETC.2019.2915589.